1. Field of the Invention
The present invention relates to a flash memory. In particular, the present invention relates to a method of erasing of a flash memory and device for erasing the same which can reduce an erase operation time and a peak current by applying a first drain bias voltage for erase to a first sector of a flash EEPROM and then applying a second drain bias voltage for erase to a second sector thereof before the first sector is completely erased.
2. Description of the Prior Art
In a conventional method of erasing chip, the entire cells of the cell array divided into a plurality of sectors are selected simultaneously, and then a bias voltage is applied to each cell. This conventional method of erase has a disadvantage that an initial erase operation current is great. In particular, as the integration of a chip becomes more higher, the drain current Vd becomes greater due to a band to band tunneling phenomenon so that a voltage drops in a drain. As a result, an erase operation is affected by the voltage drop or a noise occurs. Also, a reliability of metal lines is degraded.
An another method is to sequentially erase the sectors, after one sector is completely erased, a next sector is selected and then an erase operation is performed again. In this case, an initial peak current may be reduced, however, a time to take an erase operation is too long since the erase operation is performed whenever sectors are changed.
The value of current Id shown in FIG. 3 shows a band to band tunneling current characteristics initially generating when a drain current Vd changes after a negative voltage is applied to a gate. In order to reduce a tunneling current, a dose is controlled so as to form a drain, but too much small band to band tunneling current has a direct effect on the erase characteristics.